Symmetrical FIR filters have a sample chain with forward and reverse branches. For each filter tap, samples from both branches are combined (e.g., added together). Proper operation of the filter depends on known delay relationships between the samples in the branches of the sample chain. If the circuit is pipelined in order to increase the operating frequency of the device on which the circuit is implemented, the introduction of pipeline registers in the sample chain can affect those delay relationships.
The potential impact of pipelining may be felt in a fixed device such as an application-specific integrated circuit (ASIC) device, but may be felt even more acutely in a programmable integrated circuit device such as a programmable logic device (PLD), of which field-programmable gate arrays (FPGAs) are one type, because there frequently is a greater need in such devices for deeper pipelining to meet the operating frequency (Fmax) requirements of such devices.